AMD announces availability of 3rd Gen AMD EPYC Processors with AMD 3D V-Cache Technology

AMD has recently announced the general availability of the world’s first data center CPU using 3D die stacking, the 3rdGen AMD EPYC processors with AMD 3D V-Cache technology, formerly codenamed “Milan-X.” Built on the “Zen 3” core architecture. These processors expand the 3rdGen EPYC CPU family and can deliver up to 66 percent performance uplift across a variety of targeted technical computing workloads versus comparable, non-stacked 3rdGen AMDEPYC processors.

These new processors feature the industry’s largestL3 cache,3deliveringthe same socket, software compatibility and modern security features as 3rdGen EPYCCPUs while providing outstanding performance for technical computing workloads such as computational fluid dynamics(CFD), finite element analysis (FEA), electronic design automation(EDA)and structural analysis.

These workloads are critical design tools for companies that must model the complexities of the physical world to createsimulationsthat test and validate engineering designs for some of the world’s most innovative products.

“Building upon our momentum in the data center as well as our history of industry-firsts, 3rdGen AMD EPYC processors with AMD 3D V-Cache technology showcase the design and packaging technology enabling us to offer the industry’s first workload-tailored server processor with 3D die stacking technology,” said Dan McNamara, senior vice president and general manager, Server Business Unit, AMD.

“Our latest processors with AMD 3D V-Cache technology provide breakthrough performance for mission-critical technical computing workloads leading to better-designed products and faster time to market.” “Customers’ increased adoption of data-rich applications requires a new approach to data center infrastructure. Micron and AMD share a vision of delivering the full capability of leading DDR5 memory to high-performance data center platforms,” said Raj Hazra, senior vice president and general manager of the Compute and Networking Business Unit at Micron.

“Our deep collaboration with AMD includes readying AMD platforms for Micron's latest DDR5 solutions as well as bringing 3rdGen AMD EPYC processors with AMD 3D V-Cache technology into our own data centers, where we are already seeing up to a 40% performance improvement over 3rdGen AMD EPYC processors without AMD 3D V-Cache on select EDA workloads.”

Leading Packaging Innovations Cache size increases have been at the forefront of performance improvement, particularly for technical computing workloads relying heavily on large data sets. These workloads benefit from increased cache size, however2D chip designs have physical limitations on the amount of cache that can effectively be built on the CPU.

AMD 3D V-Cache technology solves these physical challenges by bonding the AMD “Zen 3” core to the cache module, increasing the amount of L3while minimizing latency and increasing throughput. This technology represents an innovative step forward in CPU design and packaging and enables breakthrough performance in targeted technical computing workloads.