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ARM, Synopsys enable optimized implementation of ARM Cortex-A72 processor-based SoCs with IC Compiler II

Synopsys has announced that its collaboration with ARM to bring the power of 10X throughput of IC Compiler II place and route solution is enabling superior implementation of high-frequency, power-efficient designs by delivering a Reference Implementation flow for the newly announced ARM Cortex-A72 processor.

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DQC Bureau
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Noel Hurley

Synopsys has announced that its collaboration with ARM to bring the power of 10X throughput of IC Compiler II place and route solution is enabling superior implementation of high-frequency, power-efficient designs by delivering a Reference Implementation flow for the newly announced ARM Cortex-A72 processor.

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The combination of industry-leading RTL synthesis and place-and-route solutions with a Reference Implementation flow optimized for the new CPU is already enabling engineers to deliver advanced designs for the next-generation of mobile devices.

“We have collaborated with Synopsys to ensure our mutual customers can bring innovative products to market quickly while meeting their performance, power and area targets,” said Noel Hurley, general manager, CPU Group, ARM.

“Our collaboration to create an optimized Reference Implementation with Synopsys IC Compiler II for the ARM Cortex-A72 processor will help designers take advantage of the latest technology to efficiently create products that deliver a premium mobile experience,” Hurley added.

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Reference Implementation for Cortex-A72 with Design Compiler Graphical and IC Compiler II

Based on the results of previous collaborations, including Reference Implementations for ARM Cortex-A57 and Cortex-A53 processors, the Reference Implementation for the Cortex-A72 core takes advantage of ARM POP IP in 16nm FinFET Plus process, Synopsys HPC methodology and the latest tools and features in the Galaxy Design Platform.

To achieve  upto 2.5 GHz performance in a mobile computing power envelope, the Reference Implementation includes support for Synopsys’ Design Compiler Graphical tool for RTL synthesis, IC Compiler and IC Compiler II for place and route, and PrimeTime solution for signoff and physical ECO.

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IC Compiler II is Synopsys’ latest offering in place-and-route and is a full-featured, production-ready netlist-to-GDSII implementation system delivering the highest throughput and productivity along with the best quality of results. Developed from the ground-up to deliver a leap forward in productivity, IC Compiler II is built on a new, highly efficient, multi-everything infrastructure and offers ultra-high capacity design planning, unique new clock-building technology and advanced global analytical closure techniques. These technologies enable IC Compiler II to deliver a 5X speed-up in implementation runtime along with half the iterations required to achieve target performance, together providing a 10X boost in throughput.

“This collaboration with ARM brings the power of our new place-and-route solution to new Cortex-A72 processor based designs. We have collaborated with ARM for more than 20 years to ensure that our mutual customers have the best tools and the methodology to implement their bold visions and advance the state-of-the-art of semiconductor designs,” said Antun Domic, executive vice president and general manager of the Design Group at Synopsys

Early adopters of ARM’s new suite of IP for a premium mobile experience, which includes the ARM Cortex-A72 processor, CoreLink CCI-500 interconnect, Mali-T880 GPU, Mali-V550 video processor and Mali-DP500 display processor, have been successfully using Synopsys tools and methodology to design and verify their initial designs.

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