Integrated Design Tools

It will also reduce the iterations between separate design operations- like synthesis and
place-and-route. In addition to saving design time, design efficiency also
increases the probability of first-time silicon success.

The Electronic Design Automation (EDA) industry faces a unique paradox. Each
generation of silicon process-node shrinkage results in significant increases in
design cost: at least 60% for engineering and 40% for manufacturing. At the same
time, during industry recessions, like the one we are just merging out of, sees
every player questioning the feasibility of every chip, piece of software, and
end product.

To understand the rapidly growing, almost four billion dollar EDA industry,
it helps to define what we mean for the words behind those three letters, 'EDA'
Electronic: Anything electronic-from computer chips, cellular phones,
pacemakers, controls for automobiles and satellites to the servers, routers and
switches that run the Internet. Everything made by the nearly $1 trillion
electronics industry results from designers using EDA tools and services. As
electronics become even more complex and pervasive, the EDA industry is more
vital to the continued success of the global economy.

Design:
The part of the production cycle where creativity, new ideas, ingenuity and
inspiration come to the fore. This is also where designers try to model the
behavior of their designs and analyze the complex interactions of millions of
constituent parts in their designs to ensure completeness, correctness and
manufacturability of the final product. Why? Because it is impossibly difficult,
expensive and time consuming to 'build it first and fix it later.'

Automation: Imagine the difference between designing a small house
versus designing a mile-high skyscraper. For the skyscraper you need to design
sophisticated structural, electrical, plumbing, security and environmental
systems, communications and computer networks, elevators, etc. all working
together. This is analogous to the dramatic increase in complexity that
designers must tackle in electronics today.

Pressure to lower cost

There is immense and intense pressure on chip designers to lower costs not
just at the chip development stage but even beyond at the stage of
manufacturing. My view, which I have held for a while now, is that this cannot
be ever addressed by short-term responses triggered by the cyclical nature of
the industry. But rather by a new approach to the way we have looked at and
designed EDA tools.

The most feasible solution (and a long-term one) that would result in
significantly lower costs and increased turnaround time is for the industry to
move towards tightly integrated design-tool suites. They would eliminate
iterations, addresses timing, area, power, signal integrity and yield
concurrently; and manages the high complexity designs that will be built at 90nm
and below.

Without such a system, silicon design at these process geometries will be
economically infeasible. And profitable, recession or no recession.

Why use integrated tools?

Moving beyond the business rationale, there are other reasons also as to why
I strongly advocate and feel that the time has come for integrated tool suites.
Today's designers need to consider several critical parameters and objectives,
including timing, power dissipation, signal integrity, design for testability (DFT)
and yield, concurrently.

All of these parameters are closely coupled-optimization of one affects the
others. Their interrelationships require design tools that can perform
concurrent optimization, which can only be accomplished when the tools are part
of an integrated design-tool suite and used within the right design flow.

Concurrent optimization lets the designer solve problems that affect multiple
design parameters. For example, fixing problems caused by IR drops on the chip,
which can cause intra-chip variation in supply and ground voltage levels,
results in both improved signal-integrity and timing performance.

Significance of designing tools

On the design side, efficient design reduces the iterations between separate
design operations; for example, synthesis and place-and-route. In addition to
saving design time, design efficiency also increases the probability of
first-time silicon success. With an integrated tool suite from a single vendor,
the chip's design team can comprise fewer members, since running an integrated
suite is simpler than combining and running point tools from multiple EDA
vendors.

Another economic advantage of a single-vendor integrated suite is the need
for fewer tool licenses. Finally, an EDA suite from a single vendor is better
equipped to deal with new design implementations, such as structured and
platform ASICs. These implementations are becoming increasingly popular, since
they reduce design time, design-iteration loops, risk, and cost compared to
traditional ASIC and ASSP design flows.

Reduction of costs

Manufacturing costs also profit from a design-automation flow that addresses
total design and embedded optimization. Close coupling of physical layout and
logic synthesis operations results in better chip layout, resulting in a smaller
and less expensive chip. Yield is also increased because a smaller chip results
in fewer vias and shorter average wire length, both of which reduce yield loss.

Another benefit of concurrent design-parameter optimization is reduced power
dissipation. This has several benefits, including less power-induced performance
variation across the chip, which enhances chip yield, and the use of less
expensive IC packaging, which reduces both chip and system cost.

Enhancing DFT results in higher yield through manufacturing test is another
cost-reduction advantage. Additionally, optimized test sequences reduce the time
it takes to test the chip on expensive test equipment, further reducing
manufacturing cost.

It is our experience at Magma that a properly designed EDA tool suite, using
a unified data model and embedded concurrent analysis and design-parameter
optimization, can result in the following reductions: 50%-90% in chip turnaround
time reduction, 10-15% in die size, and 15-35% in power.

To summarize, each industry goes through cycles and a common learning of
these have been that the successful ones have always been the ones who took the
long-term solution to address it. Ask me, I would say integrated is the way for
the EDA industry.

The author Rajeev Madhavan is Chairman and CEO, Magma Design Automation