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Chip Wiring Innovations for efficient computing
Applied Materials has introduced new materials engineering innovations aimed at enhancing the performance-per-watt of computer systems. These innovations enable copper wiring to scale to the 2nm logic node and beyond.
“The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption,” said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. “Applied’s newest integrated materials solution enables the industry to scale low-resistance copper wiring to the emerging angstrom nodes, while our latest low-k dielectric material simultaneously reduces capacitance and strengthens chips to take 3D stacking to new heights.”
Overcoming the Physics Challenges of Classic Moore’s Law Scaling
Today's advanced logic chips contain tens of billions of transistors connected by over 60 miles of microscopic copper wiring. Each wiring layer starts with a thin film of dielectric material, etched to create channels that are filled with copper. For decades, low-k dielectrics and copper have been the main wiring combinations in the industry, enabling improvements in scaling, performance, and power efficiency with each generation.
As the industry scales to 2nm and below, thinner dielectric material makes chips mechanically weaker. Narrowing the copper wires increases electrical resistance, which can reduce chip performance and increase power consumption.
Enhanced Low-k Dielectric Reduces Interconnect Resistance and Strengthens Chips for 3D Stacking
Applied Materials has introduced an enhanced version of its Black Diamond material. This new version, part of the Producer Black Diamond PECVD family, reduces the minimum k-value, enabling scaling to 2nm and below, and offers increased mechanical strength. This development is crucial for chipmakers and systems companies focusing on 3D logic and memory stacking. Leading logic and DRAM chipmakers are adopting the latest Black Diamond technology.
New Binary Metal Liner Enables Ultrathin Copper Wires
To scale chip wiring, chipmakers etch each layer of low-k film to create trenches, then deposit a barrier layer to prevent copper from migrating into the chip. This barrier is coated with a liner to ensure adhesion during the final copper reflow deposition sequence. As wiring scales, the barrier and liner occupy a larger volume, making it difficult to create low-resistance, void-free copper wiring.
Applied Materials has introduced its latest IMS (Integrated Materials Solution), combining six technologies in one high-vacuum system. This includes a binary metal combination of ruthenium and cobalt (RuCo), which reduces the liner thickness by 33 percent to 2nm, improves surface properties for void-free copper reflow, and reduces electrical line resistance by up to 25 percent. This solution enhances chip performance and power consumption. Many logic chipmakers are adopting the new Applied Endura Copper Barrier Seed IMS with Volta Ruthenium CVD and have started shipping to customers at the 3nm node.
Customer Insights
“While advances in patterning are driving continued device scaling, critical challenges remain in other areas including interconnect wiring resistance, capacitance, and reliability,” said Sunjung Kim, VP & Head of the Foundry Development Team at Samsung Electronics. “To help overcome these challenges, Samsung is adopting multiple materials engineering innovations that extend the benefits of scaling to the most advanced nodes.”
“The semiconductor industry must deliver dramatic improvements in energy-efficient performance to enable sustainable growth in AI computing,” said Dr. Y.J. Mii, Executive Vice President and Co-Chief Operating Officer at TSMC. “New materials that reduce interconnect resistance will play an important role in the semiconductor industry, alongside other innovations to improve overall system performance and power.”